The present invention relates to the field of semiconductor memory devices, and more particularly, to a structure having improved burn-in reliability and refresh characteristics in dynamic random access memory (DRAM) devices and a method of making it.
Metal oxide semiconductor (MOS) structures are basic electronic devices used in many integrated circuit (IC) devices. One such structure is the metal oxide semiconductor field effect transistor (MOSFET), which is typically formed in a semiconductor substrate by providing a gate structure over the substrate to define a channel region, and by forming source/drain regions on opposing sides of the channel region. To keep pace with the current trend toward maximizing the number of circuit devices contained in a single chip, integrated circuit designers continue to design IC devices with smaller and smaller feature sizes. The current state of the art for production MOSFET devices includes physical gate lengths of less than about 0.18 micron (xcexcm).
To help explain problems associated with prior art MOSFET structures, a cross section of a typical MOSFET device is shown in FIG. 1. In addition, various components of device leakage current are schematically represented. The total device leakage current, Ioff, is comprised of three major components: device off-current I1, gate leakage I2, and thermal and tunneling junction leakage xcex1I3. The device off-current I1, is determined by the physical gate length Lgate and the channel width (W) of the device, with the gate voltage Vg=0 V, the drain voltage (Vd)=power-supply voltage (Vdd), and the source voltage (Vs) to ground. The gate leakage current, I2, is determined by the gate-oxide thickness (Tox), power-supply voltage (Vdd), and the total gate area (Lgatexc3x97W). The thermal and tunneling junction leakage, I3, is determined by the operating temperature of the device and the total doping level in the substrate, which is one reason the lightly doped regions are typically placed adjacent the channel region in order to minimize junction leakage. The device off-state leakage current, Ioff, also known as the subthreshold leakage current, is a function of Lgate, temperature (T), and power-supply voltage (Vdd). The subthreshold leakage current of a MOS transistor with a physical gate length (Lgate) of less than 0.18 xcexcm exhibits what is called drain induced barrier lowering (DIBL) effect. The DIBL effect results in: (1) the leakage current changing exponentially in proportion to the drain voltage as well as the gate voltage, and (2) with the increase in the substrate bias, the drain voltage dependency increases.
As the channel lengths of MOSFET devices have been reduced below 0.18 xcexcm, MOSFETS have become more susceptible to certain problems. One common problem is increased junction leakage I3, which affects the refresh characteristics of a dynamic random access memory (DRAM) cell. DRAM is a specific category of random access memory (RAM) containing an array of individual memory cells, where each memory cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. Due to junction leakage, the stored charge must be refreshed in the capacitor on a periodic basis. Increased junction leakage leads to a premature depletion of the capacitor""s stored charge, necessitating more frequent refresh cycles in such DRAM devices.
Additionally, with gate lengths of less than 0.18 xcexcm, the width of the gate overlap region (FIG. 1) in such transistors should be as small as possible due to very tight limitations on allowable sub-threshold leakage currents. Having a smaller gate overlap region width provides an effective gate length that is as large as possible for a given physical gate length, which reduces drain-induced barrier lowering. Reducing drain-induced barrier lower improves the refresh characteristics for DRAM devices with gate overlap regions of less than 0.018 xcexcm.
However, reducing the width of the gate overlap region is not without consequences. In particular, reducing the width of the gate overlap region worsens the reliability of the DRAM device after a high voltage stress, such as experienced during burn-in. Burn-in is the application of thermal and electrical stresses for inducing the failure of marginal memory devices, those with inherent defects or defects resulting from manufacturing aberrations which cause time and stress dependent failures. During burn-in testing, ambient heat and the heat caused by the current flow under the gate structure of each MOS transistor stress the device by raising the junction temperature. This stress can lead to the premature failure of weaker devices, as the heat of burn-in causes ions in the active regions of each MOS transistor to dissipate to the point where the device can no longer function.
Generally, gate overlap widths greater than 0.02 xcexcm make DRAM devices more robust to reliability stressing, such as burn-in testing, because the gate structure has control over the inversion region directly beneath the gate structure. In such devices, the gate structure can compensate for any charges that are trapped in the gate oxide interface due to the high electrical field. That is, the gate overlap regions are less likely to degrade when high voltage is applied to the device, such as the types of voltages applied during burn-in or other manufacturing stress testing. For an NMOS device having a gate length less than 0.18 xcexcm, a gate-to-substrate voltage greater than the threshold voltage, such as experienced during burn-in, causes the formation of an inversion layer of free electrons (conducting channel) in the p-type substrate. Accordingly, a DRAM device with a gate overlap region width less than 0.018 xcexcm, which places the peak electric field outside the overlap region, results in the gate structure having less control over the inversion region, thereby further degrading device lifetime significantly. It is to be appreciated that device lifetime is generally defined as a percentage change in transconductance or drain saturation current.
To further illustrate this point, FIGS. 13a and 13b, are graphs each showing a family of drain current (Id) versus drain voltage (Vd) characteristics for different gate voltages (Vg). FIG. 13a illustrates the Id/Vd response of a poorly designed device, which shows degradation (i.e., low Id) after the first Vg sweep and is one of the main reasons for failure at burn-in. FIG. 13b, on the other hand, illustrates well-behaved Id/Vd curves for all Vg sweeps.
As mentioned previously, to reduce junction leakage DRAM devices are often designed so that their source/drain regions have a minimum dopant density. However, a lightly doped source/drain region is easy to deplete even with a small trapped-charge density at the gate oxide interface. Accordingly, device reliability decreases further in devices with gate overlap region widths less than 0.018 xcexcm by increasing the threshold voltage and transconductance after a high voltage stress, such as a device is subjected to during burn-in.
Further aggravating the problems associated with such devices with reduced overlap gate regions, is BPSG poisoning and access device n-sheet resistance. Rich BPSG (boronphosphosilicate glass) layers are needed for easy re-flow and planarity in the device. This is particularly important in stacked DRAM cell technology where the DRAM capacitor is formed in a very tall stack above the silicon substrate. Thin nitride or TEOS liners are needed for better contact processing, such as for forming precisely sized plug openings. However, TEOS liners can potentially increase the trapped states and interfacial charge density close to the source/drain regions. TEOS liners that reduce the interfacial oxide layer (gate oxide plus reoxidation) thickness in NMOS devices can permit boron from a BPSG layer to diffuse through the thin TEOS liner to compensate the n-type dopant in a source/drain region. This type of diffusion increases the n-sheet resistance of the access device. Such diffusion also decreases device reliability due to hot carriers in compensated regions now having additional states to occupy, thereby further depleting the electron density in the active area of the device.
Accordingly, for DRAM devices having MOSFETs with gate lengths less than 0.18 xcexcm and gate overlaps less than 0.018 xcexcm, there is a continued desire in the industry to improve both the device burn-in reliability and the refresh characteristics of such devices. Improving device reliability during burn-in will increase the overall production yields for such devices, thereby reducing costs and waste. Improving device refresh characteristics by providing a longer refresh cycle, reduces the overhead required to use such DRAM device, and frees up resources that can be expended in other device operations.
A memory device addressing reliability and refresh characteristics beyond that obtainable from prior art devices, as well as a method of fabricating such a device is described. In particular, the present invention addresses reliability in memory IC devices at burn-in, such for example DRAMs, having gate lengths less than 0.18 xcexcm and a gate overlap less than 0.018 xcexcm through the use of a multilayered doped conductor. The multilayered doped conductor creates a high dopant concentration in the active area close to the channel region. Because device degradation is due, at least in part, to increased trap states close to the channel region, the rich dopant layer created by the multilayered doped conductor is less susceptible to depletion of trapped charges in the oxide. This addresses device reliability at burn-in and lowers junction leakage, thereby permitting a longer period between refresh cycles.
In particular, the present invention in one embodiment discloses an integrated circuit semiconductor device having a substrate with a first surface provided with a gate structure formed thereon. Source/drain regions of the substrate have a first portion with a first dopant at a first dopant concentration on opposite sides of the gate structure. A conductor is provided adjacent the gate structure contacting one of the source/drain regions. The conductor comprises a first conductive layer having a second dopant at a second dopant concentration, and a second conductive layer having a third dopant at a third dopant concentration formed on the first conductive layer.
The present invention in another embodiment discloses an integrated circuit device having a gate electrode overlying a gate oxide layer on a surface of a semiconductor substrate, an oxide layer lying on a surface and sidewalls of the gate electrode, and spacers on sidewalls of the oxide layer. Lightly doped source/drain regions lie within the semiconductor substrate on opposite sides of the gate electrode and extend at least partially beneath the sidewalls of the oxide layer forming an overlap region. A conductor is provided adjacent one of the spacers contacting one of the source/drain regions. The conductor comprises a first conductive layer having a first dopant at a first dopant concentration, and a second conductive layer having a second dopant at a second dopant concentration formed on the first layer. The first dopant diffusivity is less than the second dopant. The first dopant forms a shallow diffusion region in the one of the source/drain regions beneath the conductor, and the second dopant forms a graded dopant concentration in the one of the source/drain regions below and adjacent the shallow diffusion region.
The present invention in still another embodiment discloses an integrated circuit device comprising a gate electrode overlying a gate oxide layer on a surface of a semiconductor substrate, an oxide layer lying on a surface and sidewalls of the gate electrode, and spacers on sidewalls of the oxide layer. Lightly doped source/drain regions are provided within the semiconductor substrate on opposite sides of the gate electrode extending partially underneath the sidewalls of the oxide layer to form an overlap region. Pocket implants are provided underlying the lightly doped source/drain regions in the semiconductor substrate. Heavily doped source/drain regions are provided lying within the semiconductor substrate adjacent to the lightly doped source/drain regions. The device further includes a conductor provided adjacent one of the spacers, which at least partially contacts one of the lightly doped source/drain regions. The conductor comprises a first conductive layer having a first dopant at a first dopant concentration, and a second conductive layer having a second dopant at a second dopant concentration formed on the first conductive layer. The first dopant diffusivity is less than the second dopant, and forms a shallow diffusion region in the source/drain regions beneath the conductor. The second dopant forms a graded dopant concentration in the lightly doped source/drain region below and adjacent the shallow diffusion region.
The present invention in yet another embodiment discloses a DRAM device having a buried capacitor memory bit cell including a substrate having a first surface, a gate structure formed on the first surface. The gate structure comprises a wordline. Lightly doped source/drain regions are formed within the substrate on opposite sides of the gate structure, and a conductor is provided adjacent the gate structure contacting one of the lightly doped source/drain regions forming a portion of a storage node. The conductor comprises a first conductive layer having a first dopant at a first dopant concentration, and a second conductive layer having a second dopant at a second dopant concentration formed on the first conductive layer.
The present invention in a further embodiment discloses a DRAM device having a buried digitline memory bit cell including a substrate having a first surface, a gate structure formed on the first surface. The gate structure comprises a wordline. Lightly doped source/drain regions are formed within the substrate on opposite sides of the gate structure, and a conductor is provided adjacent the gate structure contacting one of the lightly doped source/drain regions forming a portion of a storage node. The conductor comprises a first conductive layer having a first dopant at a first dopant concentration, and a second conductive layer having a second dopant at a second dopant concentration formed on the first conductive layer.
The present invention in another embodiment discloses a processor-based system comprising a processor, and an integrated circuit semiconductor device coupled to the processor. The integrated circuit semiconductor device comprises a substrate having a first surface, and a gate structure formed on the first surface. Source/drain regions are formed within the substrate on opposite sides of the gate structure, wherein each of source/drain regions comprise a first portion having a first dopant at a first dopant concentration. The device further includes a conductor provided adjacent the gate structure contacting one of the source/drain regions. The conductor comprises a first conductive layer having a second dopant at a second dopant concentration, and a second conductive layer having a third dopant at a third dopant concentration formed on the first conductive layer. The second dopant diffusivity is less than the third dopant, wherein the second dopant forms a shallow diffusion region in the source/drain region beneath the conductor. The shallow diffusion region has a fourth dopant concentration greater than the first dopant concentration. The third dopant provides a graded dopant concentration in the source/drain region below and adjacent the shallow diffusion region.
The present invention in another embodiment discloses a method of fabricating an integrated circuit device. The method comprises providing an opening in an insulating layer of a partially completed device to a lightly doped diffusion region. A conductor is provided in the opening and in contact with the lightly doped diffusion region. The conductor has a first conductive layer with a first dopant and a first dopant concentration, and a second conductive layer on the first conductive layer. The second conductive layer has a second dopant at a second dopant concentration.
The present invention in another embodiment, further disclosures a method of fabricating an integrated circuit device. The method comprises providing a layer of a field oxide over the surface of a semiconductor substrate, forming a gate electrode overlying the field oxide layer, and forming a capping layer having sidewalls on the surface and sidewalls of the gate electrode. The method includes implanting a first ion with a first dosage at a first energy sufficient to penetrate through the field oxide layer and into the substrate to form lightly doped source/drain regions in the semiconductor substrate adjacent the gate electrode. Spacers are then formed on sidewalls of the capping layer. An insulating layer is provided over the surface of the substrate. The method further includes providing an opening through the insulating layer to one of the lightly doped source/drain regions, and providing a first conductive layer in the opening and in contact with the one of the lightly doped source/drain regions. The first conductive layer has a first dopant and a first dopant concentration. A second conductive layer is provided on the first conductive layer. The first and second conductive layers form a conductor adjacent the spacer. The second conductive layer has a second dopant at a second dopant concentration. The first dopant diffusivity is less than the second dopant, wherein the first dopant forms by solid-state diffusion a shallow diffusion region in the lightly doped source/drain region beneath the conductor. The shallow diffusion region has a dopant concentration greater than the lightly doped source/drain region. The second dopant provides a graded dopant concentration in a portion of the lightly doped source/drain regions by diffusing below and adjacent the shallow diffusion region. The method includes continued processing to form the integrated circuit device.
In still another embodiment, a conductor for a semiconductor substrate is disclosed. The conductor comprises a first conductive layer on the semiconductor substrate, a first dopant within the first layer, a second conductive layer adjacent the first layer, and a second dopant within the second layer.
These and other features and advantages of the invention will be more fully understood from the following description of some embodiments of the invention taken together with the accompanying drawings. It is noted that the scope of the claims is defined by the recitations therein and not by the specific discussion of features and advantages set forth in the present description.